With the development from integrated circuits to large scale integrated circuits, the circuit density of the integrated circuits are increasing. In order to improve the integration of devices, the semiconductor chips generally have a multi-layer semiconductor structure. Different layers of the semiconductor structure can be electrically connected by using interconnection structures.
Referring to FIGS. 1 to 4, cross sectional structures of an existing interconnection structure corresponding to certain stages of an existing fabricating process are shown.
As shown in FIG. 1, a substrate 10 is formed. The substrate 10 includes a first to-be-connected member ma, and a low-k dielectric layer 11 covering the first to-be-connected member ma. A patterned dielectric layer 20 is formed on a surface of the substrate 10. The patterned dielectric layer 20 has a first opening 21. The first opening 21 is used for defining a position of a second to-be-connected member.
As shown in FIG. 2, the first opening 21 is filled with a dielectric material to form an oxidized dielectric layer 50. A patterned photoresist layer 60 is formed over the oxidized dielectric layer 50. The patterned photoresist layer 60 has a second opening 61 formed above the first to-be-connected member ma. The second opening 61 is used for defining a position of a plug that interconnects the first to-be-connected member ma and the second to-be-connected member.
Referencing to FIGS. 3 and 4, multiple etching processes can be performed to etch the oxide dielectric layer 50 and the low-k dielectric layer 11 to form a third opening in the low-k dielectric layer 11. The third opening includes a groove 12 for forming the second to-be-connected member and a contact hole 13 for forming the plug. Thereafter, the contact holes 13 and the trenches 12 are successively filled with the conductive material to form the plug va and the second to-be-connected member ma+1.
However, the plug va in the interconnection structure formed by using the existing fabricating method may easily deviate from the position of the first to-be-connected member ma. As such, a distance between the plug va and a device mb in the substrate 10 that is adjacent to the first to-be-connected member ma may be too small. Thus, a bridging or even a short-circuiting may be generated between the plug va and the device mb, thereby affecting the performance of the formed semiconductor device.